1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same. More particularly, the present invention relates to a semiconductor device that includes plural core chips and an interface chip to control the core chips and an information processing system including the same.
2. Description of the Related Art
A memory capacity that is required in a semiconductor device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor device that has a large memory capacity and a high operation speed as a whole.
However, this kind of semiconductor device is recognized as only one memory chip, in view of a controller. For this reason, when the plural core chips are allocated to one interface chip, how to perform an individual access to each core chip becomes a problem. In the case of the general multi-chip package, each memory chip is individually selected using a dedicated chip selection terminal (/CS) in each memory chip. Meanwhile, in the semiconductor device described above, since the chip selection terminal is provided in only the interface chip, each core chip cannot be individually selected by a chip selection signal.
In order to resolve this problem, JP-A No. 2007-157266 described above, a chip identification number is allocated to each core chip, a chip selection address is commonly provided from the interface chip to each core chip, and individual selection of each core chip is realized.
In JP-A No. 2007-157266 described above, the structure where core chips (DRAM chips) are laminated in five layers, an interface chip is laminated on the layers of the core chips, and the individual chips are connected by through silicon vias (hereinafter, “TSV”) is disclosed. This chip-lamination-type semiconductor device is finished by manufacturing the individual chips, inspecting whether defects exist in the chips, laminating the chips, and packaging the chips.
Meanwhile, the defects of the core chips may be discovered at the time of inspection after the individual chips are assembled. In this case, since the remaining core chips and the interface chip are normally operated, all of the chips do not need to be removed. Accordingly, a method in which, even though the defects exist in the partial core chips, the semiconductor device is not regarded as a defective semiconductor device, use of only the defective core chips is stopped and only the normal core chips are operated to configure a partial product, and non-defective chips are saved is required.
However, in the chip-lamination-type semiconductor device according to the related art, a chip identification number that is received from a previous stage is incremented in the core chip and is transmitted to a core chip of a next stage, and a chip identification number of each core chip is allocated. For example, the chip-lamination-type semiconductor device is configured such that chip identification numbers of (0, 0, 0) to (1, 1, 1) are necessarily allocated to core chips of eight layers. Thereby, since unique chip identification numbers are allocated to the defective core chips, the interface chip needs to manage the chip identification numbers to disable an access to the defective core chips, and control is complicated.